1. Field of the Invention
The present invention relates to an image processing apparatus, an image processing method and a computer-readable recording medium or the like, and, more particularly, to an image processing apparatus, an image processing method and a recording medium which are suitable for application to an electronic camera or the like.
2. Description of Related Art
FIG. 1 is a block diagram schematically showing the construction of a general digital electronic camera. In the digital electronic camera shown in FIG. 1, a CPU 102 (made of a microprocessor) serves to control the entire system of the digital electronic camera. A DRAM 103 is a memory element called a dynamic RAM (hereinafter referred to as the DRAM) into or from which to write or read image data, camera system programs, work data for the CPU 102 and the like. The DRAM 103 needs to perform an operation called refresh by a predetermined number of times for a predetermined time period so that the DRAM 103 can retain the contents stored therein. A block 104 is a DRAM access circuit for converting the signal outputted from the CPU 102 into a DRAM control signal. A refresh signal generating circuit 106 generates a refresh signal by producing a pulse to be outputted to a RAS (row address strobe) clock line and CAS (column address strobe) clock line which constitute DRAM control lines.
An image pickup circuit 107 is a circuit for converting an image picked up by a CCD image pickup element (not shown) into digital image data and recording the digital image data on the DRAM 103. An image display circuit 108 is a circuit for transferring image data from the DRAM 103 to a liquid crystal display panel, or converting the image data into a video signal and outputting the video signal to an external video output. An image compressing/expanding circuit 109 is a circuit for compressing image data to reduce the amount of information thereof or expanding compressed image data into data having the amount of information that is equivalent to the amount of information of the original image data. A vertical addition mixing circuit 110 is a circuit for adding vertically adjacent lines together to enable video processing of image data for two fields which are outputted from an interlaced CCD image pickup element. An image processing circuit 111 is a circuit for performing the processing of changing a size including the aspect ratio of image data on the DRAM 103, rotating an image, or changing the position of an image in the DRAM 103. A DRAM bus 113 includes a data bus, a DRAM address bus and the DRAM control lines.
The operation of the digital electronic camera shown in FIG. 1 will be described below.
First of all, the image pickup operation of the digital electronic camera will be described below. Image data formed on the CCD image pickup element is read from the image pickup circuit 107 and is temporarily recorded in the DRAM 103. Then, the vertical addition mixing circuit 110 adds together vertically adjacent lines of the image data on the DRAM 103, and again records the result in the DRAM 103. Then, the image pickup circuit 107 converts the added image data stored in the DRAM 103 into luminance color-difference image data, and again records the result in the DRAM 103. The image processing circuit 111 optimizes the aspect ratio of the luminance color-difference image data. Finally, the image data is compressed by the image compressing/expanding circuit 109, and the picked-up image is recorded as a file on a recording medium (not shown) via the DRAM bus 113.
The image display operation of the digital electronic camera will be described below. First of all, an image file is read from the recording medium by the image compressing/expanding circuit 109, and is expanded into image data in the DRAM 103. The image display circuit 108 reads the image data from the DRAM 103, and outputs the image data to a monitor (not shown). Thus, the image display operation is achieved.
To normally effect the above-described image pickup and display processing, it is necessary that the DRAM 103 be correctly refreshed in the aforesaid processing cycle and that use rights to the data bus or the DRAM 103 be correctly assigned to each image processing, refresh and the CPU 102.
The DRAM 103 needs to perform an operation called refresh by not less than a predetermined number of times for a predetermined time period. It is assumed herein that the DRAM 103 needs 1,024 refreshes per 128 msec (milliseconds).
However, the image pickup circuit 107 and the image display circuit 108 operate at horizontal and vertical periods. If refresh is performed during an image pickup operation, the image pickup operation is interrupted during the refresh. This leads to the problem that a picked-up image partly lacks data and no correct image can be obtained.
To avoid this problem, the refresh of the DRAM 103 is performed during the blanking periods of an image signal in each of an image pickup operation and an image display operation. The image pickup circuit 107 outputs a horizontal synchronizing signal. Several-microsecond periods before and after the horizontal synchronizing signal are horizontal blanking periods, during which data read from the CCD image pickup element do not appear. During such a horizontal blanking period, the DRAM 103 is refreshed because the image pickup circuit 107 does not need to record data in the DRAM 103.
When the horizontal synchronizing signal is “1”, the refresh signal generating circuit 106 generates a refresh signal of one cycle and outputs this refresh signal to both the RAS and CAS clock lines of the DRAM bus 113. It is assumed here that the period of the horizontal synchronizing signal outputted from the image pickup circuit 107 is 85 μsec (microseconds). If one refresh is performed each time one horizontal synchronizing signal is outputted, 1,506 refreshes per 128 msec are performed. This satisfies the prescribed condition of the DRAM 103, i.e., 1,024 refreshes per 128 msec.
The horizontal synchronizing signal is coupled to the hold request input of the CPU 102. While the CPU 102 is receiving the horizontal synchronizing signal, the CPU 102 temporarily stops its operation to avoid access to the DRAM 103 during refresh.
The image display circuit 108 operates in synchronism with clocks and horizontal synchronizing signals outputted from the image pickup circuit 107. The image display circuit 108 starts reading display image data several microseconds after the reception of a horizontal synchronizing signal. Assuming that the number of horizontal data of a picked-up image is equal to the number of horizontal data of a display image, the display of one horizontal line is completed before the next horizontal synchronizing signal appears. Since refresh during an image display operation is performed in synchronism with the horizontal synchronizing signal similarly to refresh during an image pickup operation, the refresh during the image display operation is performed during the horizontal blanking periods thereof.
When the image compressing/expanding circuit 109 receives a compression command, the image compressing/expanding circuit 109 compresses the data stored in the DRAM 103 into a predetermined size. The time period required for such compression processing ranges from several hundred milliseconds to several seconds according to image sizes. It is, therefore, necessary to interrupt the compression processing and refresh the DRAM 103 at intervals of a predetermined time period.
When the horizontal synchronizing signal becomes “1”, the refresh signal generating circuit 106 causes the DRAM 103 to start refreshing and outputs a signal indicating that refresh is being performed. When the image compressing/expanding circuit 109 receives this signal, the image compressing/expanding circuit 109 interrupts its processing. During this time, the refresh signal generating circuit 106 outputs a refresh signal to the DRAM 103. If the horizontal synchronizing signal again becomes “0”, the signal indicating that refresh is being performed again becomes “0” and the image compressing/expanding circuit 109 restarts the compression processing.
Similarly to the image compressing/expanding circuit 109, the vertical addition mixing circuit 110, the image processing circuit 111 and other image processing circuits operate while interrupting their processing during refresh.
However, the above-described general digital electronic camera has the following problems.
During the operation of a process such as the above-described image processing, the CPU 102 is held and temporarily stops its operation, so that the CPU 102 is not able to perform any operation other than the process. For example, during image compression, the CPU 102 is not able to perform the processing of displaying characters such as “COMPRESSING” on a liquid crystal display panel or the processing of blinking a system busy indicator lamp which indicates that it is impossible to start an image pickup operation.
In addition, since the unit time of refresh is one horizontal blanking period, refresh is performed by the number of times which is greater than the actually necessary number of times. In the aforesaid example, 1,506 refreshes per 128 msec are performed, which are approximately 1.5 times as large as the actually necessary number of refreshes per unit time, i.e., 1,024 refreshes per 128 msec. As a result, power consumption increases. Particularly during sleep, since the consumption of power due to refresh occupies a large proportion of the energy consumption of the entire camera, the above-described fact is not preferable.
Furthermore, since each of the image compressing/expanding circuit 109, the vertical addition mixing circuit 110 and the image processing circuit 111 receives refresh requests by a large number of times, the frequency with which its process is interrupted becomes higher, and the processing time period of the process becomes longer. This impairs the operability of the digital electronic camera.
During sleep or image display, since no image pickup operation needs to be performed, it is preferable to stop the supply of power to the image pickup circuit 107. However, in the above-described example, since refresh timing is generated on the basis of the operation of the image pickup circuit 107, it is impossible to stop the image pickup circuit 107 in any situation. Accordingly, it is impossible to achieve a sufficient reduction in power consumption.